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ds07-13705-6e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16lx mb90595/595g series mb90598/598g/f598/f598g/v595/v595g n description the mb90595/595g series with full-can* 1 interface and flash rom is especially designed for automotive and industrial applications. its main features are two on board can interfaces, which conform to v2.0 part a and part b, while supporting a very flexible message buffer scheme and so offering more functions than a normal full can approach. the instruction set of f 2 mc-16lx cpu core inherits an at architecture of the f 2 mc* 2 family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. the microcontroller has a 32-bit accumulator for processing long word data. the mb90595/595g series has peripheral resources of 8/10-bit a/d converters, uart (sci), extended i/o serial interface, 8/16-bit ppg timer, i/o timer (input capture (icu), output compare (ocu)) and stepping motor controller. *1: controller area network (can) - license of robert bosch gmbh *2: f 2 mc stands for fujitsu flexible microcontroller. n pac k ag e 100-pin plastic qfp (fpt-100p-m06)
mb90595/595g series 2 n features ?clock embedded pll clock multiplication circuit operating clock (pll clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 mhz, 4 mhz to 16 mhz). minimum instruction execution time: 62.5 ns (operation at oscillation of 4 mhz, four times the oscillation clock, v cc of 5.0 v) ? instruction set to optimize controller applications rich data types (bit, byte, word, long word) rich addressing mode (23 types) enhanced signed multiplication/division instruction and reti instruction functions enhanced precision calculation realized by the 32-bit accumulator ? instruction set designed for high level language (c language) and multi-task operations adoption of system stack pointer enhanced pointer indirect instructions barrel shift instructions ? program patch function (for two address pointers) ? enhanced execution speed: 4-byte instruction queue ? enhanced interrupt function: 8 levels, 34 factors ? automatic data transmission function independent of cpu operation extended intelligent i/o service function (ei 2 os): up to 10 channels ? embedded rom size and types mask rom: 128 kbytes flash rom: 128 kbytes embedded ram size: 4 kbytes (mb90v595/595g: 6 kbytes) ?flash rom supports automatic programming, embedded algorithm tm * write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm hard-wired reset vector available in order to point to a fixed boot sector erase can be performed on each block block protection with external programming voltage ? low-power consumption (stand-by) mode sleep mode (mode in which cpu operating clock is stopped) stop mode (mode in which oscillation is stopped) cpu intermittent operation mode hardware stand-by mode ? process: 0.5 m m cmos technology ? i/o port general-purpose i/o ports: 78 ports push-pull output and schmitt trigger input. programmable on each bit as i/o or signal for peripherals. ?timer watchdog timer: 1 channel 8/16-bit ppg timer: 8/16-bit 6 channels 16-bit re-load timer: 2 channels (continued)
mb90595/595g series 3 (continued) ? 16-bit i/o timer input capture: 4 channels output compare: 4 channels ? extended i/o serial interface: 1 channel ?uart0 with full-duplex double buffer (8-bit length) clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used. ?uart1 (sci) with full-duplex double buffer (8-bit length) clock asynchronized or clock synchronized serial transmission (i/o extended transmission) can be selectively used. ? stepping motor controller (4 channels) ? external interrupt circuit (8 channels) a module for starting an extended intelligent i/o service (ei 2 os) and generating an external interrupt which is triggered by an external input. ? delayed interrupt generation module: generates an interrupt request for switching tasks. ? 8/10-bit a/d converter (8 channels) 8/10-bit resolution can be selectively used. starting by an external trigger input. ? full-can interface: 1 channel conforming to version 2.0 part a and part b flexible message buffering (mailbox and fifo buffering can be mixed) ? 18-bit time-base counter ? external bus interface: maximum address space 16 mbytes *: embedded algorithm is a trademark of advanced micro devices inc.
mb90595/595g series 4 n product lineup (continued) features mb90598/598g mb90f598/f598g mb90v595/v595g classification mask rom product flash rom product evaluation product rom size 128 kbytes 128 kbytes boot block hard-wired reset vector none ram size 4 kbytes 4 kbytes 6 kbytes emulator-specific power supply * 1 ? none cpu functions the number of instructions: 351 instruction bit length: 8 bits, 16 bits instruction length: 1 byte to 7 bytes data bit length: 1 bit, 8 bits, 16 bits minimum execution time: 62.5 ns (at machine clock frequency of 16 mhz) interrupt processing time: 1.5 m s (at machine clock frequency of 16 mhz, minimum value) uart0 clock synchronized transmission (500 k/1 m/2 mbps) clock asynchronized transmission (4808/5208/9615/10417/19230/38460/62500 /500000 bps at machine clock frequency of 16 mhz) transmission can be performed by bi-directional serial transmission or by master/ slave connection. uart1(sci) clock synchronized transmission (62.5 k/125 k/250 k/500 k/1 mbps) clock asynchronized transmission (1202/2404/4808/9615/31250 bps) transmission can be performed by bi-directional serial transmission or by master/ slave connection. 8/10-bit a/d converter conversion precision: 8/10-bit can be selectively used. number of inputs: 8 one-shot conversion mode (converts selected channel once only) scan conversion mode (converts two or more successive channels and can program up to 8 channels) continuous conversion mode (converts selected channel continuously) stop conversion mode (converts selected channel and stop operation repeatedly) 8/16-bit ppg timers (6 channels) number of channels: 6 (8/16-bit 6 channels) ppg operation of 8-bit or 16-bit a pulse wave of given intervals and given duty ratios can be output. pulse interval: fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 (fsys = system clock frequency) 128 m s (fosc = 4mhz: oscillation clock frequency) 16-bit reload timer number of channels: 2 operation clock frequency: fsys/2 1 , fsys/2 3 , fsys/2 5 (fsys = system clock frequency) supports external event count function 16-bit i/o timer 16-bit output compares number of channels: 4 pin input factor: a match signal of compare register input captures number of channels: 4 rewriting a register value upon a pin input (rising, falling, or both edges)
mb90595/595g series 5 (continued) *1: it is setting of dip switch s2 when emulation pod (mb2145-507) is used. please refer to the mb2145-507 hardware manual (2.7 emulator-specific power pin) about details. *2: varies with conditions such as the operating frequency. (see section n electrical caracteristics.) features mb90598/598g mb90f598/f598g mb90v595/v595g can interface number of channels: 1 conforms to can specification version 2.0 part a and b automatic re-transmission in case of error automatic transmission responding to remote frame prioritized 16 message buffers for data and ids supports multiple messages flexible configuration of acceptance filtering: full bit compare / full bit mask / two partial bit masks supports up to 1mbps can bit timing setting: mb90xxx:tseg2 3 rsjw + 2tq mb90xxxg:tseg2 3 rsjw stepping motor controller (4 channels) four high current outputs for each channel synchronized two 8-bit pwms for each channel external interrupt circuit number of inputs: 8 started by a rising edge, a falling edge, an h level input, or an l level input. serial io clock synchronized transmission (31.25 k/62.5 k/125 k/500 k/1 mbps at system clock frequency of 16 mhz) lsb first/msb first watchdog timer reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 mhz, minimum value) flash memory supports automatic programming, embedded algorithm tm and write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm hard-wired reset vector available in order to point to a fixed boot sector in flash memory boot block configuration erase can be performed on each block block protection with external programming voltage flash writer from minato electronics inc. low-power consumption (stand-by) mode sleep/stop/cpu intermittent operation/clock timer/hardware stand-by process cmos power supply voltage for operation* 2 + 5 v 10 % package qfp-100 pga-256
mb90595/595g series 6 n pin assignment 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 vss p17/tot1 p16/tin1 p15/ppg5 p14/ppg4 p13/ppg3 p12/ppg2 p11/ppg1 p07/out3 p06/out2 p05/out1 p04/out0 p03/in3 p02/in2 p01/in1 p00/in0 vcc x1 x0 p10/ppg0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 2 3 4 5 6 7 9 8 md1 md0 p57/tot0 p56/tin0 p67/an7 p66/an6 p65/an5 p64/an4 vss p63/an3 p62/an2 p61/an1 p60/an0 avss avrl avrh avcc p55/adtg p54/int7 p53/int6 p95/int3 p94/int2 p93/int1 rst p92/int0 p91/rx p90/tx dv ss p87/pwm2m3 p86/pwm2p3 p85/pwm1m3 p84/pwm1p3 dv cc p83/pwm2m2 p82/pwm2p2 p81/pwm1m2 p80/pwm1p2 dv ss p77/pwm2m1 p76/pwm2p1 p75/pwm1m1 p74/pwm1p1 dv cc p73/pwm2m0 p72/pwm2p0 p71/pwm1m0 p70/pwm1p0 dv ss hst md2 p20 p21 p22 p23 p24 p25 p26 p27 p30 p31 p52/int5 p51/int4 p50/sin2 c p47/sck2 p46/sot2 p45/sot1 vcc p44/sck1 p43/sin1 p42/sin0 p41/sck0 p40/sot0 p37 p36 p35 p34 p33 p32 vss (top view) (fpt-100p-m06)
mb90595/595g series 7 n pin description (continued) pin no. pin name circuit type function 82 x0 a oscillator pin 83 x1 77 rst b reset input 52 hst c hardware standby input 85 to 88 p00 to p03 g general purpose io in0 to in3 inputs for the input captures 89 to 92 p04 to p07 g general purpose io out0 to out3 outputs for the output compares. 93 to 98 p10 to p15 d general purpose io ppg0 to ppg5 outputs for the programmable pulse generators 99 p16 d general purpose io tin1 tin input for the 16-bit reload timer 1 100 p17 d general purpose io tot1 tot output for the 16-bit reload timer 1 1 to 8 p20 to p27 g general purpose io 9 to 10 p30 to p31 g general purpose io 12 to 16 p32 to p36 g general purpose io 17 p37 d general purpose io 18 p40 g general purpose io sot0 sot output for uart 0 19 p41 g general purpose io sck0 sck input/output for uart 0 20 p42 g general purpose io sin0 sin input for uart 0 21 p43 g general purpose io sin1 sin input for uart 1 22 p44 g general purpose io sck1 sck input/output for uart 1 24 p45 g general purpose io sot1 sot output for uart 1 25 p46 g general purpose io sot2 sot output for the serial io 26 p47 g general purpose io sck2 sck input/output for the serial io
mb90595/595g series 8 (continued) pin no. pin name circuit type function 28 p50 d general purpose io sin2 sin input for the serial io 29 to 32 p51 to p54 d general purpose io int4 to int7 external interrupt input for int4 to int7 33 p55 d general purpose io adtg input for the external trigger of the a/d converter 38 to 41 p60 to p63 e general purpose io an0 to an3 inputs for the a/d converter 43 to 46 p64 to p67 e general purpose io an4 to an7 inputs for the a/d converter 47 p56 d general purpose io tin0 tin input for the 16-bit reload timer 0 48 p57 d general purpose io tot0 tot output for the 16-bit reload timer 0 54 to 57 p70 to p73 f general purpose io pwm1p0 pwm1m0 pwm2p0 pwm2m0 output for stepper motor controller channel 0 59 to 62 p74 to p77 f general purpose io pwm1p1 pwm1m1 pwm2p1 pwm2m1 output for stepper motor controller channel 1 64 to 67 p80 to p83 f general purpose io pwm1p2 pwm1m2 pwm2p2 pwm2m2 output for stepper motor controller channel 2 69 to 72 p84 to p87 f general purpose io pwm1p3 pwm1m3 pwm2p3 pwm2m3 output for stepper motor controller channel 3 74 p90 d general purpose io tx tx output for can interface 75 p91 d general purpose io rx rx input for can interface
mb90595/595g series 9 (continued) pin no. pin name circuit type function 76 p92 d general purpose io int0 external interrupt input for int0 78 to 80 p93 to p95 d general purpose io int1 to int3 external interrupt input for int1 to int3 58, 68 dv cc ? dedicated power supply pins for the high current output buffers (pin no. 54 to 72) 53, 63, 73 dv ss ? dedicated ground pins for the high current output buffers (pin no. 54 to 72) 34 av cc power supply dedicated power supply pin for the a/d converter 37 av ss power supply dedicated ground pin for the a/d converter 35 avrh power supply upper reference voltage input for the a/d converter 36 avrl power supply lower reference voltage input for the a/d converter 49, 50 md0 md1 c operating mode selection input pins. these pins should be con- nected to v cc or v ss . 51 md2 h operating mode selection input pin. this pin should be connected to v cc or v ss . 27 c ? external capacitor pin. a capacitor of 0.1 m f should be connected to this pin and v ss . 23, 84 v cc power supply power supply pins (5.0 v). 11, 42, 81 v ss power supply ground pins (0.0 v).
mb90595/595g series 10 n i/o circuit type (continued) circuit type circuit remarks a ? oscillation feedback resistor: 1 m w approx. b ? hysteresis input with pull-up resistor: 50 k w approx. c ? hysteresis input d ?cmos output ? cmos hysteresis input e ?cmos output ? cmos hysteresis input ? analog input x1 hard, soft standby control x0 clock input hys r r hys r hys r p-ch n-ch v cc analog input hys r p-ch n-ch v cc
mb90595/595g series 11 (continued) circuit type circuit remarks f ? cmos high current output ? cmos hysteresis input g ?cmos output ? cmos hysteresis input ? ttl input (mb90f598/f598g, only in flash mode) h ? hysteresis input pull-down resistor: 50 w approx. (except mb90f598/f598g) hys high current r p-ch n-ch v cc hys ttl t r r p-ch n-ch v cc hys r r
mb90595/595g series 12 n handling devices (1) make sure that the voltage not exceed the maximum rating (to avoid a latch-up). in cmos ics, a latch-up phenomenon is caused when an voltage exceeding v cc or an voltage below v ss is applied to input or output pins or a voltage exceeding the rating is applied across v cc and v ss . when a latch-up is caused, the power supply current may be dramatically increased causing resultant thermal break-down of devices. to avoid the latch-up, make sure that the voltage not exceed the maximum rating. in turning on/turning off the analog power supply, make sure the analog power voltage (av cc , avrh, dv cc ) and analog input voltages not exceed the digital voltage (v cc ). (2) treatment of unused pins unused input pins left open may cause abnormal operation, or latch-up leading to permanent damage. unused input pins should be pulled up or pulled down through at least 2 k w resistance. unused input/output pins may be left open in output state, but if such pins are in input state they should be handled in the same way as input pins. (3) using external clock in using the external clock, drive x0 pin only and leave x1 pin unconnected. (4) power supply pins (vcc/vss) in products with multiple v cc or v ss pins, pins with the same potential are internally connected in the device to avoid abnormal operations including latch-up. however, you must connect the pins to an external power and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating (see the figure below.) make sure to connect v cc and v ss pins via lowest impedance to power lines. it is recommended to provide a bypass capacitor of around 0.1 m f between v cc and v ss pins near the device. x0 x1 mb90595/595g series using external clock open vcc vss vss vcc vss vcc mb90595/595g series vcc vss vcc vss
mb90595/595g series 13 (5) pull-up/down resistors the mb90595 series does not support internal pull-up/down resistors. use external components where needed. (6) crystal oscillator circuit noises around x0 or x1 pins may cause abnormal operations. make sure to provide bypass capacitors via shortest distance from x0, x1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure that lines of oscillation circuit not cross the lines of other circuits. a printed circuit board artwork surrounding the x0 and x1 pins with ground area for stabilizing the operation is highly recommended. (7) turning-on sequence of power supply to a/d converter and analog inputs make sure to turn on the a/d converter power supply (av cc , avrh, avrl) and analog inputs (an0 to an7) after turning-on the digital power supply (v cc ). turn-off the digital power after turning off the a/d converter supply and analog inputs. in this case, make sure that the voltage does not exceed avrh or av cc (turning on/off the analog and digital power supplies simulta- neously is acceptable). (8) connection of unused pins of a/d converter connect unused pins of a/d converter to av cc = v cc , av ss = avrh = dv cc = v ss . (9) n.c. pin the n.c. (internally connected) pin must be opened for use. (10) notes on energization to prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 m s or more (0.2 v to 2.7 v). (11) indeterminate outputs from ports 0 and 1 (mb90598/f598/v595/v595g only) during oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on, the outputs from ports 0 and 1 become following state. ?if rst pin is h, the outputs become indeterminate. ?if rst pin is l, the outputs become high-impedance. pay attention to the port output timing shown as follow. oscillation setting time *2 power-on reset *1 vcc (power-supply pin) ponr (power-on reset) signal rst (external asynchronous reset) signal rst (internal reset) signal oscillation clock signal ka (internal operation clock a) signal kb (internal operation clock b) signal port (port output) signal period of indeterminated *1:power-on reset time: period of clock frequency 2 17 (clock frequency of 16 mhz: 8.19 ms) *2:oscillation setting time: period of clock frequency 2 18 (clock frequency of 16 mhz: 16.38ms) rst pin is h
mb90595/595g series 14 (12) initialization the device contains internal registers which are initialized only by a power-on reset. to initialize these registers, please turn on the power again. (13) directions of div a, ri and divw a, rwi instructions in the signed multiplication and division instructions (div a, ri and divw a, rwi), the value of the corre- sponding bank register (dtb, adb, usb, ssb) is set in 00 h . if the values of the corresponding bank register (dtb,adb,usb,ssb) are set to other than 00 h , the remainder by the execution result of the instruction is not stored in the register of the instruction operand. (14) using realos the use of ei 2 os is not possible with the realos real time operating system. (15) caution on operations during pll clock mode if the pll clock mode is selected in the microcontroller, it may attempt to continue the operation using the free- running frequency of the automatic oscillating circuit in the pll circuitry even if the oscillator is out of place or the clock input is stopped. performance of this operation, however, cannot be guaranteed. oscillation setting time *2 power-on reset *1 vcc (power-supply pin) ponr (power-on reset) signal rst (external asynchronous reset) signal rst (internal reset) signal oscillation clock signal ka (internal operation clock a) signal kb (internal operation clock b) signal port (port output) signal high-impedance *1:power-on reset time: period of clock frequency 2 17 (clock frequency of 16 mhz: 8.19 ms) *2:oscillation setting time: period of clock frequency 2 18 (clock frequency of 16 mhz: 16.38ms) rst pin is l
mb90595/595g series 15 n block diagram ram 4 k rom/flash uart0 prescaler serial i/o prescaler 10-bit adc 8 ch 16-bit reload timer 2 ch 16-bit clock controller 16-bit input capture 4 ch 16-bit output compare 4 ch can controller external interrupt 8/16-bit ppg 6 ch f 2 mc-16lx cpu f 2 mc-16 bus x0,x1 rst hst sot0 sck0 sin0 sck2 sot2 sin2 avcc avss an0 to an7 avrh avrl adtg tin0, tin1 tot0, tot1 in0 to in3 out0 to out3 ppg0 to ppg5 rx tx int0 to int7 uart1 prescaler sot1 sck1 sin1 (sci) 128 k smc 4ch pwm1m0 to pwm1m3 pwm1p0 to pwm1p3 pwm2m0 to pwm2m3 pwm2p0 to pwm2p3 dvcc0, dvcc1 dvss0 to dvss2 io timer 8 ch
mb90595/595g series 16 n memory space the memory space of the mb90595 series is shown below memory space map note: the rom data of bank ff is reflected in the upper address of bank 00, realizing effective use of the c compiler small model. the lower 16-bit of bank ff and the lower 16-bit of bank 00 are assigned to the same address, enabling reference of the table on the rom without stating far. for example, if an attempt has been made to access 00c000 h , the contents of the rom at ffc000 h are accessed. since the rom area of the ff bank exceeds 48 kbytes, the whole area cannot be reflected in the image for the 00 bank. the rom data at ff4000 h to ffffff h looks, therefore, as if it were the image for 004000 h to 00ffff h . thus, it is recommended that the rom data table be stored in the area of ff4000 h to ffffff h . mb90v595/v595g mb90598/598g/ f598/f598g ffffff h ff0000 h rom (ff bank) ffffff h ff0000 h rom (ff bank) feffff h fe0000 h rom (fe bank) feffff h fe0000 h rom (fe bank) fdffff h fd0000 h rom (fd bank) fcffff h fc0000 h rom (fc bank) 00ffff h 004000 h rom (image of ff bank) 00ffff h 004000 h rom (image of ff bank) 001fff h 001900 h peripheral 001fff h 001900 h peripheral 0018ff h 000100 h ram 6 k 0010ff h 000100 h ram 4 k 0000bf h 000000 h peripheral 0000bf h 000000 h peripheral
mb90595/595g series 17 n i/o map (continued) address register abbreviation access peripheral initial value 00 h port 0 data register pdr0 r/w port 0 xxxxxxxx b 01 h port 1 data register pdr1 r/w port 1 xxxxxxxx b 02 h port 2 data register pdr2 r/w port 2 xxxxxxxx b 03 h port 3 data register pdr3 r/w port 3 xxxxxxxx b 04 h port 4 data register pdr4 r/w port 4 xxxxxxxx b 05 h port 5 data register pdr5 r/w port 5 xxxxxxxx b 06 h port 6 data register pdr6 r/w port 6 xxxxxxxx b 07 h port 7 data register pdr7 r/w port 7 xxxxxxxx b 08 h port 8 data register pdr8 r/w port 8 xxxxxxxx b 09 h port 9 data register pdr9 r/w port 9 _ _ xxxxxx b 0a h to 0f h reserved 10 h port 0 direction register ddr0 r/w port 0 0 0 0 0 0 0 0 0 b 11 h port 1 direction register ddr1 r/w port 1 0 0 0 0 0 0 0 0 b 12 h port 2 direction register ddr2 r/w port 2 0 0 0 0 0 0 0 0 b 13 h port 3 direction register ddr3 r/w port 3 0 0 0 0 0 0 0 0 b 14 h port 4 direction register ddr4 r/w port 4 0 0 0 0 0 0 0 0 b 15 h port 5 direction register ddr5 r/w port 5 0 0 0 0 0 0 0 0 b 16 h port 6 direction register ddr6 r/w port 6 0 0 0 0 0 0 0 0 b 17 h port 7 direction register ddr7 r/w port 7 0 0 0 0 0 0 0 0 b 18 h port 8 direction register ddr8 r/w port 8 0 0 0 0 0 0 0 0 b 19 h port 9 direction register ddr9 r/w port 9 _ _ 0 0 0 0 0 0 b 1a h reserved 1b h analog input enable register ader r/w port 6, a/d 1 1 1 1 1 1 1 1 b 1c h to 1f h reserved 20 h serial mode control register 0 umc0 r/w uart0 0 0 0 0 0 1 0 0 b 21 h serial status register 0 usr0 r/w 0 0 0 1 0 0 0 0 b 22 h serial input/output data register 0 uidr0/ uodr0 r/w xxxxxxxx b 23 h rate and data register 0 urd0 r/w 0 0 0 0 0 0 0 x b 24 h serial mode register 1 smr1 r/w uart1 0 0 0 0 0 0 0 0 b 25 h serial control register 1 scr1 r/w 0 0 0 0 0 1 0 0 b 26 h serial input/output data register 1 sidr1/ sodr1 r/w xxxxxxxx b 27 h serial status register 1 ssr1 r/w 0 0 0 0 1 _ 0 0 b 28 h uart1 prescaler control register u1cdcr r/w 0 _ _ _ 1 1 1 1 b
mb90595/595g series 18 (continued) address register abbreviation access peripheral initial value 29 h to 2a h reserved 2b h serial io prescaler scdcr r/w serial io 0 _ _ _ 1 1 1 1 b 2c h serial mode control register (low-order) smcs r/w _ _ _ _ 0 0 0 0 b 2d h serial mode control register (high-order) smcs r/w 0 0 0 0 0 0 1 0 b 2e h serial data register sdr r/w xxxxxxxx b 2f h edge selector ses r/w _ _ _ _ _ _ _ 0 b 30 h external interrupt enable register enir r/w external interrupt 0 0 0 0 0 0 0 0 b 31 h external interrupt request register eirr r/w xxxxxxxx b 32 h external interrupt level register elvr r/w 0 0 0 0 0 0 0 0 b 33 h external interrupt level register elvr r/w 0 0 0 0 0 0 0 0 b 34 h a/d control status register 0 adcs0 r/w a/d converter 0 0 0 0 0 0 0 0 b 35 h a/d control status register 1 adcs1 r/w 0 0 0 0 0 0 0 0 b 36 h a/d data register 0 adcr0 r xxxxxxxx b 37 h a/d data register 1 adcr1 r/w 0 0 0 0 1 _ xx b 38 h ppg0 operation mode control register ppgc0 r/w 16-bit program- mable pulse generator 0/1 0 _ 0 0 0 _ _ 1 b 39 h ppg1 operation mode control register ppgc1 r/w 0 _ 0 0 0 0 0 1 b 3a h ppg0, 1 output pin control register ppg01 r/w 0 0 0 0 0 0 _ _ b 3b h reserved 3c h ppg2 operation mode control register ppgc2 r/w 16-bit program- mable pulse generator 2/3 0 _ 0 0 0 _ _ 1 b 3d h ppg3 operation mode control register ppgc3 r/w 0 _ 0 0 0 0 0 1 b 3e h ppg2, 3 output pin control register ppg23 r/w 0 0 0 0 0 0 _ _ b 3f h reserved 40 h ppg4 operation mode control register ppgc4 r/w 16-bit program- mable pulse generator 4/5 0 _ 0 0 0 _ _ 1 b 41 h ppg5 operation mode control register ppgc5 r/w 0 _ 0 0 0 0 0 1 b 42 h ppg4, 5 output pin control register ppg45 r/w 0 0 0 0 0 0 _ _ b 43 h reserved 44 h ppg6 operation mode control register ppgc6 r/w 16-bit program- mable pulse generator 6/7 0 _ 0 0 0 _ _ 1 b 45 h ppg7 operation mode control register ppgc7 r/w 0 _ 0 0 0 0 0 1 b 46 h ppg6, 7 output pin control register ppg67 r/w 0 0 0 0 0 0 _ _ b 47 h reserved 48 h ppg8 operation mode control register ppgc8 r/w 16-bit program- mable pulse generator 8/9 0 _ 0 0 0 _ _ 1 b 49 h ppg9 operation mode control register ppgc9 r/w 0 _ 0 0 0 0 0 1 b 4a h ppg8, 9 output pin control register ppg89 r/w 0 0 0 0 0 0 _ _ b 4b h reserved
mb90595/595g series 19 (continued) address register abbreviation access peripheral initial value 4c h ppga operation mode control register ppgca r/w 16-bit programmable pulse generator a/b 0 _ 0 0 0 _ _ 1 b 4d h ppgb operation mode control register ppgcb r/w 0 _ 0 0 0 0 0 1 b 4e h ppga, b output pin control register ppgab r/w 0 0 0 0 0 0 _ _ b 4f h reserved 50 h timer control status register 0 tmcsr0 r/w 16-bit reload timer 0 0 0 0 0 0 0 0 0 b 51 h timer control status register 0 tmcsr0 r/w _ _ _ _ 0 0 0 0 b 52 h timer 0/reload register 0 tmr0/ tmrlr0 r/w xxxxxxxx b 53 h timer 0/reload register 0 tmr0/ tmrlr0 r/w xxxxxxxx b 54 h timer control status register 1 tmcsr1 r/w 16-bit reload timer 1 0 0 0 0 0 0 0 0 b 55 h timer control status register 1 tmcsr1 r/w _ _ _ _ 0 0 0 0 b 56 h timer register 1/reload register 1 tmr1/ tmrlr1 r/w xxxxxxxx b 57 h timer register 1/reload register 1 tmr1/ tmrlr1 r/w xxxxxxxx b 58 h output compare control status register 0 ocs0 r/w output compare 0/1 0 0 0 0 _ _ 0 0 b 59 h output compare control status register 1 ocs1 r/w _ _ _ 0 0 0 0 0 b 5a h output compare control status register 2 ocs2 r/w output compare 2/3 0 0 0 0 _ _ 0 0 b 5b h output compare control status register 3 ocs3 r/w _ _ _ 0 0 0 0 0 b 5c h input capture control status register 0/1 ics01 r/w input capture 0/1 0 0 0 0 0 0 0 0 b 5d h input capture control status register 2/3 ics23 r/w input capture 2/3 0 0 0 0 0 0 0 0 b 5e h pwm control register 0 pwc0 r/w stepping motor controller 0 0 0 0 0 0 _ _ 0 b 5f h reserved 60 h pwm control register 1 pwc1 r/w stepping motor controller 1 0 0 0 0 0 _ _ 0 b 61 h reserved 62 h pwm control register 2 pwc2 r/w stepping motor controller 2 0 0 0 0 0 _ _ 0 b 63 h reserved 64 h pwm control register 3 pwc3 r/w stepping motor controller 3 0 0 0 0 0 _ _ 0 b 65 h reserved 66 h timer data register (low-order) tcdt r/w io timer 0 0 0 0 0 0 0 0 b 67 h timer data register (high-order) tcdt r/w 0 0 0 0 0 0 0 0 b 68 h timer control status register tccs r/w 0 0 0 0 0 0 0 0 b 69 h to 6e h reserved
mb90595/595g series 20 (continued) address register abbreviation access peripheral initial value 6f h rom mirror function selection register romm r/w rom mirror _ _ _ _ _ _ _ 1 b 70 h pwm1 compare register 0 pwc10 r/w stepping motor controller 0 xxxxxxxx b 71 h pwm2 compare register 0 pwc20 r/w xxxxxxxx b 72 h pwm1 select register 0 pws10 r/w _ _ 0 0 0 0 0 0 b 73 h pwm2 select register 0 pws20 r/w _ 0 0 0 0 0 0 0 b 74 h pwm1 compare register 1 pwc11 r/w stepping motor controller 1 xxxxxxxx b 75 h pwm2 compare register 1 pwc21 r/w xxxxxxxx b 76 h pwm1 select register 1 pws11 r/w _ _ 0 0 0 0 0 0 b 77 h pwm2 select register 1 pws21 r/w _ 0 0 0 0 0 0 0 b 78 h pwm1 compare register 2 pwc12 r/w stepping motor controller 2 xxxxxxxx b 79 h pwm2 compare register 2 pwc22 r/w xxxxxxxx b 7a h pwm1 select register 2 pws12 r/w _ _ 0 0 0 0 0 0 b 7b h pwm2 select register 2 pws22 r/w _ 0 0 0 0 0 0 0 b 7c h pwm1 compare register 3 pwc13 r/w stepping motor controller 3 xxxxxxxx b 7d h pwm2 compare register 3 pwc23 r/w xxxxxxxx b 7e h pwm1 select register 3 pws13 r/w _ _ 0 0 0 0 0 0 b 7f h pwm2 select register 3 pws23 r/w _ 0 0 0 0 0 0 0 b 80 h to 8f h can controller. refer to section about can controller 90 h to 9d h reserved 9e h program address detection control status register pacsr r/w address match detection function 0 0 0 0 0 0 0 0 b 9f h delayed interrupt/request register dirr r/w delayed interrupt _ _ _ _ _ _ _ 0 b a0 h low-power mode control register lpmcr r/w low power controller 0 0 0 1 1 0 0 0 b a1 h clock selection register ckscr r/w low power controller 1 1 1 1 1 1 0 0 b a2 h to a7 h reserved a8 h watchdog timer control register wdtc r/w watchdog timer xxxxx 1 1 1 b a9 h time base timer control register tbtc r/w time base timer 1 _ _ 0 0 1 0 0 b aa h to ad h reserved ae h flash memory control status register (mb90f598/f598g only. otherwise reserved) fmcs r/w flash memory 0 0 0 x 0 0 0 0 b af h reserved
mb90595/595g series 21 (continued) address register abbreviation access peripheral initial value b0 h interrupt control register 00 icr00 r/w interrupt controller 0 0 0 0 0 1 1 1 b b1 h interrupt control register 01 icr01 r/w 0 0 0 0 0 1 1 1 b b2 h interrupt control register 02 icr02 r/w 0 0 0 0 0 1 1 1 b b3 h interrupt control register 03 icr03 r/w 0 0 0 0 0 1 1 1 b b4 h interrupt control register 04 icr04 r/w interrupt controller 0 0 0 0 0 1 1 1 b b5 h interrupt control register 05 icr05 r/w 0 0 0 0 0 1 1 1 b b6 h interrupt control register 06 icr06 r/w 0 0 0 0 0 1 1 1 b b7 h interrupt control register 07 icr07 r/w 0 0 0 0 0 1 1 1 b b8 h interrupt control register 08 icr08 r/w 0 0 0 0 0 1 1 1 b b9 h interrupt control register 09 icr09 r/w 0 0 0 0 0 1 1 1 b ba h interrupt control register 10 icr10 r/w 0 0 0 0 0 1 1 1 b bb h interrupt control register 11 icr11 r/w 0 0 0 0 0 1 1 1 b bc h interrupt control register 12 icr12 r/w 0 0 0 0 0 1 1 1 b bd h interrupt control register 13 icr13 r/w 0 0 0 0 0 1 1 1 b be h interrupt control register 14 icr14 r/w 0 0 0 0 0 1 1 1 b bf h interrupt control register 15 icr15 r/w 0 0 0 0 0 1 1 1 b c0 h to ff h reserved 1900 h reload register l prll0 r/w 16-bit programmable pulse generator 0/1 xxxxxxxx b 1901 h reload register h prlh0 r/w xxxxxxxx b 1902 h reload register l prll1 r/w xxxxxxxx b 1903 h reload register h prlh1 r/w xxxxxxxx b 1904 h reload register l prll2 r/w 16-bit programmable pulse generator 2/3 xxxxxxxx b 1905 h reload register h prlh2 r/w xxxxxxxx b 1906 h reload register l prll3 r/w xxxxxxxx b 1907 h reload register h prlh3 r/w xxxxxxxx b 1908 h reload register l prll4 r/w 16-bit programmable pulse generator 4/5 xxxxxxxx b 1909 h reload register h prlh4 r/w xxxxxxxx b 190a h reload register l prll5 r/w xxxxxxxx b 190b h reload register h prlh5 r/w xxxxxxxx b 190c h reload register l prll6 r/w 16-bit programmable pulse generator 6/7 xxxxxxxx b 190d h reload register h prlh6 r/w xxxxxxxx b 190e h reload register l prll7 r/w xxxxxxxx b 190f h reload register h prlh7 r/w xxxxxxxx b
mb90595/595g series 22 (continued) address register abbreviation access peripheral initial value 1910 h reload register l prll8 r/w 16-bit programmable pulse generator 8/9 xxxxxxxx b 1911 h reload register h prlh8 r/w xxxxxxxx b 1912 h reload register l prll9 r/w xxxxxxxx b 1913 h reload register h prlh9 r/w xxxxxxxx b 1914 h reload register l prlla r/w 16-bit programmable pulse generator a/b xxxxxxxx b 1915 h reload register h prlha r/w xxxxxxxx b 1916 h reload register l prllb r/w 16-bit programmable pulse generator a/b xxxxxxxx b 1917 h reload register h prlhb r/w xxxxxxxx b 1918 h to 191f h reserved 1920 h input capture register 0 (low-order) ipcp0 r input capture 0/1 xxxxxxxx b 1921 h input capture register 0 (high-order) ipcp0 r xxxxxxxx b 1922 h input capture register 1 (low-order) ipcp1 r xxxxxxxx b 1923 h input capture register 1 (high-order) ipcp1 r xxxxxxxx b 1924 h input capture register 2 (low-order) ipcp2 r input capture 2/3 xxxxxxxx b 1925 h input capture register 2 (high-order) ipcp2 r xxxxxxxx b 1926 h input capture register 3 (low-order) ipcp3 r xxxxxxxx b 1927 h input capture register 3 (high-order) ipcp3 r xxxxxxxx b 1928 h output compare register 0 (low-order) occp0 r/w output compare 0/1 xxxxxxxx b 1929 h output compare register 0 (high-order) occp0 r/w xxxxxxxx b 192a h output compare register 1 (low-order) occp1 r/w xxxxxxxx b 192b h output compare register 1 (high-order) occp1 r/w xxxxxxxx b
mb90595/595g series 23 (continued) note: initial value of _ represents unused bit; x represents unknown value. addresses in the rage 0000 h to 00ff h , which are not listed in the table, are reserved for the primary functions of the mcu. a read access to these reserved addresses results in reading x, and any write access should not be performed. address register abbreviation access peripheral initial value 192c h output compare register 2 (low-order) occp2 r/w output compare 2/3 xxxxxxxx b 192d h output compare register 2 (high-order) occp2 r/w xxxxxxxx b 192e h output compare register 3 (low-order) occp3 r/w xxxxxxxx b 192f h output compare register 3 (high-order) occp3 r/w xxxxxxxx b 1930 h to 19ff h reserved 1a00 h to 1aff h can controller. refer to section about can controller 1b00 h to 1bff h can controller. refer to section about can controller 1c00 h to 1eff h reserved 1ff0 h program address detection register 0 (low-order) padr0 r/w address match detection function xxxxxxxx b 1ff1 h program address detection register 0 (middle-order) xxxxxxxx b 1ff2 h program address detection register 0 (high-order) xxxxxxxx b 1ff3 h program address detection register 1 (low-order) padr1 r/w xxxxxxxx b 1ff4 h program address detection register 1 (middle-order) xxxxxxxx b 1ff5 h program address detection register 1 (high-order) xxxxxxxx b 1ff6 h to 1fff h reserved
mb90595/595g series 24 n can controller the can controller has the following features: ? conforms to can specification version 2.0 part a and b - supports transmission/reception in standard frame and extended frame formats ? supports transmission of data frames by receiving remote frames ? 16 transmitting/receiving message buffers - 29-bit id and 8-byte data - multi-level message buffer configuration ? provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as 1d acceptance mask - two acceptance mask registers in either standard frame format or extended frame formats ? bit rate programmable from 10 kbit/s to 2 mbit/s (when input clock is at 16 mhz) list of control registers (continued) address register abbreviation access initial value 000080 h message buffer valid register bvalr r/w 00000000 00000000 b 000081 h 000082 h transmit request register treqr r/w 00000000 00000000 b 000083 h 000084 h transmit cancel register tcanr w 00000000 00000000 b 000085 h 000086 h transmit complete register tcr r/w 00000000 00000000 b 000087 h 000088 h receive complete register rcr r/w 00000000 00000000 b 000089 h 00008a h remote request receiving register rrtrr r/w 00000000 00000000 b 00008b h 00008c h receive overrun register rovrr r/w 00000000 00000000 b 00008d h 00008e h receive interrupt enable register rier r/w 00000000 00000000 b 00008f h 001b00 h control status register csr r/w, r 00---000 0----0-1 b 001b01 h 001b02 h last event indicator register leir r/w -------- 000-0000 b 001b03 h 001b04 h receive/transmit error counter rtec r 00000000 00000000 b 001b05 h 001b06 h bit timing register btr r/w -1111111 11111111 b 001b07 h
mb90595/595g series 25 (continued) address register abbreviation access initial value 001b08 h ide register ider r/w xxxxxxxx xxxxxxxx b 001b09 h 001b0a h transmit rtr register trtrr r/w 00000000 00000000 b 001b0b h 001b0c h remote frame receive waiting register rfwtr r/w xxxxxxxx xxxxxxxx b 001b0d h 001b0e h transmit interrupt enable register tier r/w 00000000 00000000 b 001b0f h 001b10 h acceptance mask select register amsr r/w xxxxxxxx xxxxxxxx b 001b11 h 001b12 h xxxxxxxx xxxxxxxx b 001b13 h 001b14 h acceptance mask register 0 amr0 r/w xxxxxxxx xxxxxxxx b 001b15 h 001b16 h xxxxx--- xxxxxxxx b 001b17 h 001b18 h acceptance mask register 1 amr1 r/w xxxxxxxx xxxxxxxx b 001b19 h 001b1a h xxxxx--- xxxxxxxx b 001b1b h
mb90595/595g series 26 list of message buffers (id registers) (continued) address register abbreviation access initial value 001a00 h to 001a1f h general-purpose ram -- r/w xxxxxxxx b to xxxxxxxx b 001a20 h id register 0 idr0 r/w xxxxxxxx xxxxxxxx b 001a21 h 001a22 h xxxxx--- xxxxxxxx b 001a23 h 001a24 h id register 1 idr1 r/w xxxxxxxx xxxxxxxx b 001a25 h 001a26 h xxxxx--- xxxxxxxx b 001a27 h 001a28 h id register 2 idr2 r/w xxxxxxxx xxxxxxxx b 001a29 h 001a2a h xxxxx--- xxxxxxxx b 001a2b h 001a2c h id register 3 idr3 r/w xxxxxxxx xxxxxxxx b 001a2d h 001a2e h xxxxx--- xxxxxxxx b 001a2f h 001a30 h id register 4 idr4 r/w xxxxxxxx xxxxxxxx b 001a31 h 001a32 h xxxxx--- xxxxxxxx b 001a33 h 001a34 h id register 5 idr5 r/w xxxxxxxx xxxxxxxx b 001a35 h 001a36 h xxxxx--- xxxxxxxx b 001a37 h 001a38 h id register 6 idr6 r/w xxxxxxxx xxxxxxxx b 001a39 h 001a3a h xxxxx--- xxxxxxxx b 001a3b h 001a3c h id register 7 idr7 r/w xxxxxxxx xxxxxxxx b 001a3d h 001a3e h xxxxx--- xxxxxxxx b 001a3f h
mb90595/595g series 27 (continued) address register abbreviation access initial value 001a40 h id register 8 idr8 r/w xxxxxxxx xxxxxxxx b 001a41 h 001a42 h xxxxx--- xxxxxxxx b 001a43 h 001a44 h id register 9 idr9 r/w xxxxxxxx xxxxxxxx b 001a45 h 001a46 h xxxxx--- xxxxxxxx b 001a47 h 001a48 h id register 10 idr10 r/w xxxxxxxx xxxxxxxx b 001a49 h 001a4a h xxxxx--- xxxxxxxx b 001a4b h 001a4c h id register 11 idr11 r/w xxxxxxxx xxxxxxxx b 001a4d h 001a4e h xxxxx--- xxxxxxxx b 001a4f h 001a50 h id register 12 idr12 r/w xxxxxxxx xxxxxxxx b 001a51 h 001a52 h xxxxx--- xxxxxxxx b 001a53 h 001a54 h id register 13 idr13 r/w xxxxxxxx xxxxxxxx b 001a55 h 001a56 h xxxxx--- xxxxxxxx b 001a57 h 001a58 h id register 14 idr14 r/w xxxxxxxx xxxxxxxx b 001a59 h 001a5a h xxxxx--- xxxxxxxx b 001a5b h 001a5c h id register 15 idr15 r/w xxxxxxxx xxxxxxxx b 001a5d h 001a5e h xxxxx--- xxxxxxxx b 001a5f h
mb90595/595g series 28 list of message buffers (dlc registers and data registers) (continued) address register abbreviation access initial value 001a60 h dlc register 0 dlcr0 r/w ----xxxx b 001a61 h 001a62 h dlc register 1 dlcr1 r/w ----xxxx b 001a63 h 001a64 h dlc register 2 dlcr2 r/w ----xxxx b 001a65 h 001a66 h dlc register 3 dlcr3 r/w ----xxxx b 001a67 h 001a68 h dlc register 4 dlcr4 r/w ----xxxx b 001a69 h 001a6a h dlc register 5 dlcr5 r/w ----xxxx b 001a6b h 001a6c h dlc register 6 dlcr6 r/w ----xxxx b 001a6d h 001a6e h dlc register 7 dlcr7 r/w ----xxxx b 001a6f h 001a70 h dlc register 8 dlcr8 r/w ----xxxx 001a71 h 001a72 h dlc register 9 dlcr9 r/w ----xxxx b 001a73 h 001a74 h dlc register 10 dlcr10 r/w ----xxxx b 001a75 h 001a76 h dlc register 11 dlcr11 r/w ----xxxx b 001a77 h 001a78 h dlc register 12 dlcr12 r/w ----xxxx b 001a79 h 001a7a h dlc register 13 dlcr13 r/w ----xxxx b 001a7b h 001a7c h dlc register 14 dlcr14 r/w ----xxxx b 001a7d h 001a7e h dlc register 15 dlcr15 r/w ----xxxx b 001a7f h 001a80 h to 001a87 h data register 0 (8 bytes) dtr0 r/w xxxxxxxx b to xxxxxxxx b
mb90595/595g series 29 (continued) address register abbreviation access initial value 001a88 h to 001a8f h data register 1 (8 bytes) dtr1 r/w xxxxxxxx b to xxxxxxxx b 001a90 h to 001a97 h data register 2 (8 bytes) dtr2 r/w xxxxxxxx b to xxxxxxxx b 001a98 h to 001a9f h data register 3 (8 bytes) dtr3 r/w xxxxxxxx b to xxxxxxxx b 001aa0 h to 001aa7 h data register 4 (8 bytes) dtr4 r/w xxxxxxxx b to xxxxxxxx b 001aa8 h to 001aaf h data register 5 (8 bytes) dtr5 r/w xxxxxxxx b to xxxxxxxx b 001ab0 h to 001ab7 h data register 6 (8 bytes) dtr6 r/w xxxxxxxx b to xxxxxxxx b 001ab8 h to 001abf h data register 7 (8 bytes) dtr7 r/w xxxxxxxx b to xxxxxxxx b 001ac0 h to 001ac7 h data register 8 (8 bytes) dtr8 r/w xxxxxxxx b to xxxxxxxx b 001ac8 h to 001acf h data register 9 (8 bytes) dtr9 r/w xxxxxxxx b to xxxxxxxx b 001ad0 h to 001ad7 h data register 10 (8 bytes) dtr10 r/w xxxxxxxx b to xxxxxxxx b 001ad8 h to 001adf h data register 11 (8 bytes) dtr11 r/w xxxxxxxx b to xxxxxxxx b 001ae0 h to 001ae7 h data register 12 (8 bytes) dtr12 r/w xxxxxxxx b to xxxxxxxx b 001ae8 h to 001aef h data register 13 (8 bytes) dtr13 r/w xxxxxxxx b to xxxxxxxx b 001af0 h to 001af7 h data register 14 (8 bytes) dtr14 r/w xxxxxxxx b to xxxxxxxx b 001af8 h to 001aff h data register 15 (8 bytes) dtr15 r/w xxxxxxxx b to xxxxxxxx b
mb90595/595g series 30 n interrupt map interrupt source ei 2 os clear interrupt vector interrupt control register number address number address reset n/a # 08 ffffdc h int9 instruction n/a # 09 ffffd8 h exception n/a # 10 ffffd4 h can rx n/a # 11 ffffd0 h icr00 0000b0 h can tx/ns n/a # 12 ffffcc h external interrupt (int0/int1) *1 # 13 ffffc8 h icr01 0000b1 h time base timer n/a # 14 ffffc4 h 16-bit reload timer 0 *1 # 15 ffffc0 h icr02 0000b2 h 8/10-bit a/d converter *1 # 16 ffffbc h i/o timer n/a # 17 ffffb8 h icr03 0000b3 h external interrupt (int2/int3) *1 # 18 ffffb4 h serial i/o *1 # 19 ffffb0 h icr04 0000b4 h external interrupt (int4/int5) *1 # 20 ffffac h input capture 0 *1 # 21 ffffa8 h icr05 0000b5 h 8/16-bit ppg 0/1 n/a # 22 ffffa4 h output compare 0 *1 # 23 ffffa0 h icr06 0000b6 h 8/16-bit ppg 2/3 n/a # 24 ffff9c h external interrupt (int6/int7) *1 # 25 ffff98 h icr07 0000b7 h input capture 1 *1 # 26 ffff94 h 8/16-bit ppg 4/5 n/a # 27 ffff90 h icr08 0000b8 h output compare 1 *1 # 28 ffff8c h 8/16-bit ppg 6/7 n/a # 29 ffff88 h icr09 0000b9 h input capture 2 *1 # 30 ffff84 h 8/16-bit ppg 8/9 n/a # 31 ffff80 h icr10 0000ba h output compare 2 *1 # 32 ffff7c h input capture 3 *1 # 33 ffff78 h icr11 0000bb h 8/16-bit ppg a/b n/a # 34 ffff74 h output compare 3 *1 # 35 ffff70 h icr12 0000bc h 16-bit reload timer 1 *1 # 36 ffff6c h uart 0 rx *2 # 37 ffff68 h icr13 0000bd h uart 0 tx *1 # 38 ffff64 h uart 1 rx *2 # 39 ffff60 h icr14 0000be h uart 1 tx *1 # 40 ffff5c h flash memory n/a # 41 ffff58 h icr15 0000bf h delayed interrupt n/a # 42 ffff54 h
mb90595/595g series 31 *1: the interrupt request flag is cleared by the ei 2 os interrupt clear signal. *2: the interrupt request flag is cleared by the ei 2 os interrupt clear signal. a stop request is available. n/a:the interrupt request flag is not cleared by the ei 2 os interrupt clear signal. notes: for a peripheral module with two interrupt for a single interrupt number, both interrupt request flags are cleared by the ei 2 os interrupt clear signal. at the end of ei 2 os, the ei 2 os clear signal will be asserted for all the interrupt flags assigned to the same interrupt number. if one interrupt flag starts the ei 2 os and in the meantime another interrupt flag is set by hardware event, the later event is lost because the flag is cleared by the ei 2 os clear signal caused by the first event. so it is recommended not to use the ei 2 os for this interrupt number. if ei 2 os is enabled, ei 2 os is initiated when one of the two interrupt signals in the same interrupt control register (icr) is asserted. this means that different interrupt sources share the same ei 2 os descriptor which should be unique for each interrupt source. for this reason, when one interrupt source uses the ei 2 os, the other interrupt should be disabled.
mb90595/595g series 32 n electrical characteristics 1. absolute maximum ratings (v ss = av ss = 0.0 v) *1: av cc , avrh, avrl and dv cc shall not exceed v cc . avrh and avrl shall not exceed av cc . also, avrl shall never exceed avrh. *2: v i and v o should not exceed v cc + 0.3v. v i should not exceed the specified ratings. however if the maximum current to/from an input is limited by some means with external components, the i clamp rating supersedes the v i rating. *3: the maximum output current is a peak value for a corresponding pin. *4: average output current is an average current value observed for a 100 ms period for a corresponding pin. *5: total average current is an average current value observed for a 100 ms period for all corresponding pins. (continued) parameter symbol rating unit remarks min max power supply voltage v cc v ss - 0.3 v ss + 6.0 v av cc v ss - 0.3 v ss + 6.0 v v cc = av cc * 1 avrh , avrl v ss - 0.3 v ss + 6.0 v av cc 3 avrh/l, avrh 3 avrl * 1 dv cc v ss - 0.3 v ss + 6.0 v v cc 3 dv cc input voltage v i v ss - 0.3 v ss + 6.0 v * 2 output voltage v o v ss - 0.3 v ss + 6.0 v * 2 maximum clamp current i clamp - 2.0 2.0 ma *6 maximum total clamp current ? ? i clamp ? ? 20 ma *6 l level max. output current i ol1 15 ma normal output * 3 l level avg. output current i olav1 4 ma normal output, average value * 4 l level max. output current i ol2 40 ma high current output * 3 l level avg. output current i olav2 30 ma high current output, average value * 4 l level max. overall output current ? i ol1 100 ma total normal output l level max. overall output current ? i ol2 330 ma total high current output l level avg. overall output current ? i olav1 50ma total normal output, average value * 5 l level avg. overall output current ? i olav2 250ma total high current output, average value * 5 h level max. output current i oh1 - 15 ma normal output * 3 h level avg. output current i ohav1 - 4 ma normal output, average value * 4 h level max. output current i oh2 - 40 ma high current output * 3 h level avg. output current i ohav2 - 30 ma high current output, average value * 4 h level max. overall output current ? i oh1 - 100 ma total normal output h level max. overall output current ? i oh2 - 330 ma total high current output h level avg. overall output current ? i ohav1 - 50 ma total normal output, average value * 5 h level avg. overall output current ? i ohav2 - 250 ma total high current output, average value * 5 power consumption p d 500 mw mb90f598/f598g 400 mw mb90598/598g operating temperature t a - 40 + 85 c storage temperature t stg - 55 + 150 c
mb90595/595g series 33 (continued) *6: applicable to pins : p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p70 to p77, p80 to p87, p90 to p95 use within recommended operating conditions. use at dc voltage (current) . the + b signal should always be applied with a limiting resistance placed between the + b signal and the microcontroller. the value of the limiting resistance should be set so that when the + b signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. note that when the microcontroller drive current is low, such as in the power saving modes, the + b input potential may pass through the protective diode and increase the potential at the v cc pin, and this may affect other devices. note that if a + b signal is input when the microcontroller current is off (not fixed at 0 v) , the power supply is provided from the pins, so that incomplete operation may result. note that if the + b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on result. care must be taken not to leave the + b input pin open. note that analog system input/output pins other than the a/d input pins (lcd drive pins, comparator input pins, etc.) cannot accept + b signal input. sample recommended circuits : note: average output current = operating current operating efficiency warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. p-ch n-ch v cc r ? input/output equivalent circuits + b input (0 v to 16 v) limiting resistance protective diode
mb90595/595g series 34 2. recommended conditions (v ss = av ss = 0.0 v) *: use a ceramic capacitor or a capacitor with equivalent frequency characteristics. the smoothing capacitor to be connected to the v cc pin must have a capacitance value higher than c s . warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min typ max power supply voltage v cc av cc 4.5 5.0 5.5 v under normal operation 3.0 ? 5.5 v maintains ram data in stop mode smooth capacitor c s 0.022 0.1 1.0 m f* operating temperature t a C40 ? +85 c c c s ? c pin connection diagram
mb90595/595g series 35 3. dc characteristics (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = - 40 c to + 85 c) (continued) parameter sym- bol pin name condition value unit remarks min typ max input h voltage v ihs cmos hysteresis input pin 0.8 v cc ? v cc +0.3 v v ihm md input pin v cc C 0.3 ? v cc +0.3 v input l voltage v ils cmos hysteresis input pin v ss C 0.3 ? 0.2 v cc v v ilm md input pin v ss C 0.3 ? v ss +0.3 v output h voltage v oh1 output pins except p70 to p87 v cc = 4.5 v, i oh1 = C4.0 ma v cc C 0.5 v output h voltage v oh2 p70 to p87 v cc = 4.5 v, i oh2 = C30.0 ma v cc C 0.5 v output l voltage v ol1 output pins except p70 to p87 v cc = 4.5 v, i ol1 = 4.0 ma 0.4v output l voltage v ol2 p70 to p87 v cc = 4.5 v, i ol2 = 30.0 ma 0.5v input leak current i il v cc = 5.5 v, v ss < v i < v cc C5 5 m a power supply current * i cc v cc v cc = 5.0 v 10%, internal frequency: 16 mhz, at normal operating 3560ma mb90598, mb90598g 5090ma mb90f598 4060ma mb90f598g i ccs v cc = 5.0 v 10%, internal frequency: 16 mhz, at sleep 1118ma i cts v cc = 5.0 v 1%, internal frequency: 2 mhz, at timer mode 0.30.6ma i cch v cc = 5.0 v 10%, at stop, t a = 25 c 20 m a i cch2 v cc = 5.0 v 10%, at hardware stand- by mode, t a = 25 c 20 m a mb90598, mb90598g, mb90f598 50100 m a mb90f598g
mb90595/595g series 36 (continued) (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = - 40 c to + 85 c) * : the power supply current testing conditions are when using the external clock. parameter sym- bol pin name condition value unit remarks min typ max input capacity c in other than c, av cc , av ss , avrh, avrl, v cc , v ss , dv cc , dv ss , p70 to p87 515pf p70 to p87 15 30 pf pull-up resistance r up rst 2550100k w pull-down resistance r down md2 25 50 100 k w
mb90595/595g series 37 4. ac characteristics (1) clock timing (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = - 40 c to + 85 c) *: frequency deviation indicates the maximum frequency difference from the target frequency when using a multi- plied clock. example of oscillation circuit parameter symbol pin name value unit remarks min typ max oscillation frequency f c x0, x1 3 16 mhz oscillation cycle time t cyl x0, x1 62.5 333 ns frequency deviation with pll * d f5% input clock pulse width p wh , p wl x0 10 ns duty ratio is about 30 to 70%. input clock rise and fall time t cr , t cf x0 5 ns when using external clock machine clock frequency f cp 1.516mhz machine clock cycle time t cp 62.5 666 ns + a c ent r al f r equen c y f o - a d f a fo ------ 100% = t cyl p wh t cf p wl t cr 0.8 v cc 0.2 v cc x0 ? clock timing x0 x1 r c1 c2
mb90595/595g series 38 ac characteristics are set to the measured reference voltage values below. 16 5.5 4.5 3.0 1.5 8 power supply voltage v cc (v) machine clock f cp (mhz) guaranteed operation range guaranteed pll operation range ? guaranteed operation range 16 12 4 9 8 3 4 8 16 machine clock f cp (mhz) oscillation frequency f c (mhz) ? oscillation frequency and machine clock frequency 4 3 2 1 1/2 (pll off) ? input signal waveform hysteresis input pin 0.8 v cc 0.2 v cc ? output signal waveform output pin 2.4 v 0.8 v
mb90595/595g series 39 (2) reset and hardware standby input (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = - 40 c to + 85 c) *1: t cp represents one cycle time of the machine clock. no reset can fully initialize the flash memory if it is performing the automatic algorithm. *2: oscillation time of oscillator is time that the amplitude reached the 90%. in the crystal oscillator, the oscillation time is between several ms to tens of ms. in far / ceramic oscillator, the oscillation time is between hundreds of m s to several ms. in the external clock, the oscillation time is 0 ms. parameter symbol pin name value unit remarks min max reset input time t rstl rst 16 t cp * 1 ns under normal operation oscillation time of oscillator* 2 + 16 t cp * 1 ms in stop mode hardware standby input time t hstl hst 16 t cp * 1 ns under normal operation oscillation time of oscillator* 2 + 16 t cp * 1 ms in stop mode 0.2 v cc rst hst t rstl , t hstl 0.2 v cc under normal operation t rstl , t hstl 0.6v cc 0.6v cc rst hst x0 16 t cp internal operation clock internal reset oscillation time of oscillator oscillation setting time instruction execution 90 % of amplitude in stop mode
mb90595/595g series 40 (3)power on reset (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = - 40 c to + 85 c) *: v cc must be kept lower than 0.2 v before power-on. notes: the above values are used for creating a power-on reset. some registers in the device are initialized only upon a power-on reset. to initialize these register, turn on the power supply using the above values. parameter symbol pin name condition value unit remarks min max power on rise time t r v cc 0.05 30 ms * power off time t off v cc 50 ms due to repetitive operation t r 2.7 v 0.2 v v cc 0.2 v 0.2 v t off sudden changes in the power supply voltage may cause a power-on reset. to change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. in this case, change the supply voltage with the pll clock not used. if the voltage drop is 1 v or fewer per second, however, you can use the pll clock. v cc v ss 3 v ram data being held it is recommended to keep the rising speed of the supply voltage at 50 mv/ms or slower.
mb90595/595g series 41 (4) uart0/1, serial i/o timing (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = - 40 c to + 85 c) notes: ac characteristic in clk synchronized mode. c l is load capacity value of pins when testing. t cp is the machine cycle (unit: ns). parameter symbol pin name condition value unit remarks min max serial clock cycle time t scyc sck0 to sck2 internal clock oper- ation output pins are c l = 80 pf + 1 ttl. 8 t cp ns sck t sot delay time t slov sck0 to sck2, sot0 to sot2 C80 80 ns valid sin t sck - t ivsh sck0 to sck2, sin0 to sin2 100 ns sck - t valid sin hold time t shix sck0 to sck2, sin0 to sin2 60 ns serial clock h pulse width t shsl sck0 to sck2 external clock oper- ation output pins are c l = 80 pf + 1 ttl. 4 t cp ns serial clock l pulse width t slsh sck0 to sck2 4 t cp ns sck t sot delay time t slov sck0 to sck2, sot0 to sot2 150 ns valid sin t sck - t ivsh sck0 to sck2, sin0 to sin2 60 ns sck - t valid sin hold time t shix sck0 to sck2, sin0 to sin2 60 ns sck 2.4 v t scyc 0.8 v sot 0.8 v 2.4 v 0.8 v t slov sin 0.2 v cc 0.8 v cc t ivsh 0.2 v cc 0.8 v cc t shix ? internal shift clock mode
mb90595/595g series 42 (5) timer input timing (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = - 40 c to + 85 c) parameter symbol pin name condition value unit remarks min max input pulse width t tiwh tin0, tin1 4 t cp ns t tiwl in0 to in3 sck 0.8 v cc t slsh 0.2 v cc sot 0.8 v 2.4 v t slov sin 0.2 v cc 0.8 v cc t ivsh 0.2 v cc 0.8 v cc t shix 0.8 v cc 0.2 v cc t shsl ? external shift clock mode 0.2 v cc 0.8 v cc t tiwh 0.2 v cc 0.8 v cc t tiwl ? timer input timing
mb90595/595g series 43 (6) trigger input timing (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = - 40 c to + 85 c) (7) slew rate high current outputs (mb90598, mb90598g, mb90f598g only) (v cc = 5.0 v 10 %, v ss = av ss = 0.0 v, t a = - 40 c to + 85 c) parameter symbol pin name condition value unit remarks min max input pulse width t trgh t trgl int0 to int7, adtg 5 t cp ns under normal operation 1 m s in stop mode parameter symbol pin name condition value unit remarks min typ max output rise/fall time t r2 t f2 port p70 to p77, port p80 to p87 15 40 150 ns 0.2 v cc 0.8 v cc t trgh 0.2 v cc 0.8 v cc t trgl ? trigger input timing ? slew rate output timing v h v l t r2 v h v l t f2 v h = v ol2 + 0.1 (v oh2 - v ol2 ) v l = v ol2 + 0.9 (v oh2 - v ol2 )
mb90595/595g series 44 5. a/d converter (v cc = av cc = 5.0 v 10%, v ss = av ss = 0.0 v,3.0 v avrh - avrl, t a = - 40 c to +85 c) * : when not operating a/d converter, this is the current (v cc = av cc = avrh = 5.0 v) when the cpu is stopped. parameter sym- bol pin name value unit remarks min typ max resolution 10 bit conversion error 5.0 lsb nonlinearity error 2.5 lsb differential linearity error 1.9 lsb zero transition voltage v ot an0 to an7 avrl - 3.5 avrl +0.5 avrl + 4.5 mv full scale transition voltage v fst an0 to an7 avrh - 6.5 avrh - 1.5 avrh + 1.5 mv conversion time 352t cp ns sampling time 64t cp ns analog port input current i ain an0 to an7 - 10 10 m a analog input voltage range v ain an0 to an7 avrl avrh v reference voltage range avrh avrl + 3.0 av cc v avrl 0 avrh - 3.0 v power supply current i a av cc 5ma i ah av cc 5 m a* reference voltage current i r avrh 400 600 m a mb90v595, mb90v595g, mb90f598, mb90f598g 140 600 m a mb90598, mb90598g i rh avrh 5 m a* offset between input chan- nels an0 to an7 4 lsb
mb90595/595g series 45 6. a/d converter glossary resolution: analog changes that are identifiable with the a/d converter linearity error: the deviation of the straight line connecting the zero transition point (00 0000 0000 ? 00 0000 0001) with the full-scale transition point (11 1111 1110 ? 11 1111 1111) from actual conversion characteristics differential linearity error: the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value total error: the total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error. (continued) total error 3ff 3fe 3fd 004 003 002 001 analog input avrl avrh actual conversion value d i g i t a l o u t p u t v nt (measured value) 0.5 lsb actual conversion characteristics theoretical characteristics 0.5 lsb {1 lsb (n C 1) + 0.5 lsb} [v] avrh C avrl 1024 1 lsb = (theoretical value) v ot (theoretical value) = avrl + 0.5 lsb[v] v fst (theoretical value) = avrh C 1.5 lsb[v] total error for digital output n [lsb] v nt C {1 lsb (n C 1) + 0.5 lsb} 1 lsb = v nt : voltage at a transition of digital output from (n C 1) to n
mb90595/595g series 46 (continued) 7. notes on using a/d converter select the output impedance value for the external circuit of analog input according to the following conditions,: ? output impedance values of the external circuit of 15 k w or lower are recommended. ? when capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. when the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient (sampling period = 4.00 m s @machine clock of 16 mhz). ?error the smaller the | avrh - avrl |, the greater the error would become relatively. linearity error 3ff 3fe 3fd 004 003 002 001 analog input avrl avrh analog input avrl avrh actual conversion characteristics v ot (measured value) v fst (measured value) actual conversion value v nt {1 lsb (n C 1)+ v ot } theoretical characteristics d i g i t a l o u t p u t d i g i t a l o u t p u t differential linearity error theoretical characteristics v (n + 1)t (measured value) actual conversion value v nt (measured value) actual conversion value linearity error of digital output n v ot: voltage at transition of digital output from 000 h to 001 h v fst : voltage at transition of digital output from 3fe h to 3ff h [lsb] v nt C {1 lsb (n C 1) + v ot } 1 lsb = [v] v fst C v ot 1022 = 1 lsb C 1 lsb [lsb] v (n + 1)t C v nt 1 lsb = differential linearity error of digital n n + 1 n n C 1 n C 2 ? equipment of analog input circuit model comparator analog input 30 pf max 3.2 k w max
mb90595/595g series 47 8. flash memory ? erase and programming performance parameter condition value unit remarks min typ max sector erase time t a = + 25 c, v cc = 5.0 v ? 1 15 s mb90f598g excludes 00h programming prior erasure ? 1.5 30 s mb90f598 chip erase time ? 5 ? s mb90f598g excludes 00h programming prior ? 10.5 ? s mb90f598 word (16-bit) programming time ? 16 3600 m s mb90f598g excludes system-level overhead ? 32 1000 m s mb90f598 erase/program cycle ? 10000 ?? cycle
mb90595/595g series 48 n example characteristics h level output voltage l level input voltage h level input voltage/l level input voltage (hysteresis input) i oh1 [ma] v oh1 [v] v oh1 C i oh1 (vcc = 4.5 v, t a = +25?c) 4 3.5 3 2.5 2 1.5 1 0.5 0 -2.0 -10.0 -6.0 -8.0 -4.0 0.0 4.5 5 v oh2 [v] i oh2 [ma] v oh2 C i oh2 (vcc = 4.5 v, t a = +25?c) 0 -40 -30 -20 -10 4 3.5 3 2.5 2 1.5 1 0.5 0 4.5 5 i ol1 [ma] v ol1 [mv] v ol1 C i ol1 (vcc = 4.5 v, t a = +25?c) 600 500 400 300 200 100 0 2.0 10.0 8.0 4.0 0.0 6.0 v ol2 [mv] i ol2 [ma] v ol2 C i ol2 (vcc = 4.5 v, t a = +25?c) 500 400 300 200 100 0 600 40 30 20 10 0 vcc [v] v in [v] v in C v cc (t a = +25?c) 5 4 3 2 1 0 6 5 4 3 v ih v il
mb90595/595g series 49 supply current v cc [v] i cc [ma] i cc C v cc (t a = +25?c) 35 30 25 20 15 10 5 0 3.0 7.0 5.0 6.0 4.0 2.0 40 45 fcp = 16 mhz fcp = 12 mhz fcp = 8 mhz fcp = 4 mhz fcp = 2 mhz i ccs [ma] v cc [v] i ccs C v cc (t a = +25?c) 2.0 7.0 6.0 4.0 3.0 16 14 12 10 8 6 4 2 0 5.0 fcp = 16 mhz fcp = 12 mhz fcp = 8 mhz fcp = 4 mhz fcp = 2 mhz v cc [v] i cts [ m a] i cts C v cc (fcp = f2 mhz, t a = +25?c) 600 500 400 300 200 100 0 3.0 7.0 6.0 4.0 2.0 5.0 i cct [ m a] v cc [v] i cch C v cc (t a = +25?c) 18 16 12 6 4 0 20 3.0 7.0 6.0 4.0 2.0 5.0 14 10 8 2 vcc [v] i cct2 [ m a] i cct2 C v cc 50 40 30 20 10 0 6.0 5.0 4.0 2.0 100 90 80 70 60 3.0 7.0 (mb90f598g only, t a = 25?c)
mb90595/595g series 50 n ordering information part number package remarks mb90598pf mb90598gpf mb90f598pf mb90f598gpf 100-pin plastic qfp (fpt-100p-m06) mb90v595cr mb90v595gcr 256-pin ceramic pga (pga-256c-a01) for evaluation
mb90595/595g series 51 n package dimensions 100-pin plastic qfp (fpt-100p-m06) dimensions in mm (inches) c 2001 fujitsu limited f100008s-c-4-4 1 30 31 50 51 80 81 100 20.00?.20(.787?008) 23.90?.40(.941?016) 14.00?.20 (.551?008) 17.90?.40 (.705?016) index 0.65(.026) 0.32?.05 (.013?002) m 0.13(.005) "a" 0.17?.06 (.007?002) 0.10(.004) details of "a" part 0~8 (.035?006) 0.88?.15 (.031?008) 0.80?.20 0.25(.010) 3.00 +0.35 ?.20 +.014 ?008 .118 (mounting height) 0.25?.20 (.010?008) (stand off)
mb90595/595g series fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f 0201 ? fujitsu limited printed in japan

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